| 摘要 |
<p>PURPOSE:To perform the transfer of data synchronously between one main data collection/transfer circuit and plural asynchronous slave data collection/ transfer circuits, by performing the transfer of the data after detecting a state where all of the slave data collection/transfer circuits are possible to perform the transfer of the data. CONSTITUTION:After the data from the data collection/transfer circuit 1 is set at a communication circuit 2, an interruption signal is outputted from the communication circuit 2 to communication circuits (5-1-5-n). The data collection/transfer circuit possible to perform the transfer out of the data collection/ transfer circuits (6-1-6-n) outputs a ready signal to a ready signal detecting circuit 3 via a corresponding communication circuit. When the reception of the ready signals from all of the communicating circuits (5-1-5-n) is detected, the ready signal detecting circuit 3 outputs the above information to a clock generating circuit 4, and the clock generating circuit 4 outputs a clock to the communicating circuit 2 and the communicating circuits (5-1-5-n). The transfer of the data between the data collection/transfer circuit 1 that is a master and the data collection/transfer circuits (6-1-6-n) that are slaves are performed simultaneously.</p> |
