| 摘要 |
PURPOSE:To miniaturize a decrement counter requiring parity check and to make the circuit small in size, by constituting a parity predict circuit with read- only memories. CONSTITUTION:The decrement counter 10 outputs a counter output of 8 bits via output lines 101-108. An ROM41 plays a role of a conventional parity predicting circuit and its readout output is led to an input of a gate 62. The gate 62 constitutes a conventional expectation parity check storage circuit together with an expectation parity flip-flop 61 and an output of an FF61 is led to an input of a parity check circuit 70. The circuit 70 compares an expectation parity bit stored in the expectation parity FF61 with an actual parity bit produced in response to the output of the decerment counter 10 to detect the parity error of the decrement counter 10, and its detected output is led to a parity error flip- flop 51 and stored. |
