| 摘要 |
PURPOSE:To minimize an error rate by limiting the input period to the higher harmonic removing means of a multiplication output to 1/2 tome slot period of the latter half, and removing a waveform distortion due to the impedance mismatching of an input by-phase signal with a simple circuit constitution. CONSTITUTION:An input bi-pass signal S(t) inputted from an input terminal 31 is inputted through a limiter amplifier 32 to a delaying circuit 33 and an exclusive 'or' circuit 34, multiplied with a bi-phase signal S(t-tau) delayed only by a time tau of one time slot and outputs an output signal (f). An AND circuit 40 receives the signal (f) and a clock (g) reproduced by a clock reproducing circuit 37 and inputs a signal (h) limited only to the latter half time slot period of the signal (f) to an analog integrator 35. The integrator 35 resets by the fall of a signal (g) or a resetting signal from a limit signal generating circuit 39, and an identifying circuit 36 compares and identifies an output (i) with a threshold value. An identification result (j) is inputted to a differential decoding circuit 38 and demodulating data (k) are outputted.
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