Semiconductor memory device

摘要

In the case of a semiconductor memory device having a matrix of memory cells arranged in rows and columns, there is provided a plurality of groups (1a, 1b, 1c) of memory cells which are subdivided by segmenting the matrix in the direction of the columns. In order that a particular memory cell can be accessed, memory cell group selection lines (14a, 14b, 14c) for each individual one of the groups are provided for the selection of one of the plurality of groups of these memory cells and row decoders (4) are provided for each individual one of the rows for decoding row-address information for a particular memory cell. In order to reduce the power consumption, priority word lines (15) are provided, each of which is connected to the output of the associated row decoder (4). AND gates (16a, 16b, 16c) in each case supply a logical product of a group enable signal located on the memory cell group selection line and of a row enable signal from the row coders. Group word lines (3a, 3b, 3c) exist in each case per group and per row and serve for receiving the logical product output signal for each of the AND gates. Access is made to the particular memory cell by the product output signal of the corresponding one of the group word lines. Furthermore, column decoders are provided for decoding column-address information for the particular memory cell which is being accessed. In this case, ... Original abstract incomplete. <IMAGE>