| 摘要 |
PURPOSE:To reduce serial shift operation required to read out response data of a circuit to be tested by latching data at an input terminal to a latch circuit only when the data at a parallel input terminal differs from expected value data. CONSTITUTION:If data at a parallel input terminal 10 differs from expected value data stored in a latch circuit 1b, an output of an Ex NOR circuit 19 goes to a L level. When a negative clock is given to a test clock terminal 22, a positive clock is given to an output of a NOR circuit 20. When no clock is given to a clock terminal 5 in this case, the positive clock is fed to an enable terminal of a latch circuit 1a and the data at the input terminal 10 is latched in the latch circuit 1a. Since the serial shift operation is only implemented at the end of the expected value of consecutive 0s or 1s, the serial shift operation in testing the circuit to be tested is reduced. |
