发明名称 DIGITAL SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To accurately reproduce digital information by eliminating the reduction in the eye aperture rate, by branching a detection signal into two through an HPF and adding further them through a delay circuit, a comparator and an LPF. CONSTITUTION:A detection signal A from a detection circuit is branched into two after an HPF filter 21 and given to a delay circuit 2 and a comparator 23. The signal inputted to the comparator 23 is compared with a reference voltage Vpi1 and becomes binary information and inputted to an adder circuit 25 through an LPF 24. The output of the LPF 24 becomes a signal B being the inversion of the level fluctuation component of the detection signal A. A delay circuit 22 retards the input signal so that the phase is coincident with that of the signal B and gives the result to the adder circuit 25. A signal C eliminating the level fluctuation component from the detection signal A is outputted from the adder circuit 25, it is compared with a reference voltage Vpi2 by a comparator 26, outputted as binary information and becomes a reproducing signal.
申请公布号 JPS63308767(A) 申请公布日期 1988.12.16
申请号 JP19870145649 申请日期 1987.06.10
申请人 SHARP CORP 发明人 YASUE HIDETAKA;SAGAWA MANABU;KOMODA TOMOHISA;MUKAI ATSUO;KAKIWAKI NARIMITSU
分类号 G11B20/10 主分类号 G11B20/10
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