| 摘要 |
PURPOSE:To quicken access by precharging a bit line pair to a lower potential than a half the power potential so as to increase the margin of reading of storage information. CONSTITUTION:FETs Q9, 10, 21, 22, 2 are turned on at the leading of a signal phi1, bit lines BL, the inverse of BL are short-circuited to be 1/2Vcc, a signal phi6 is trailed at the same time, a Q25 is turned off, a reference voltage V0 of the circuit 1 reaches 0, a Q23 is turned off and the line BL is interrupted from a level guarantee circuit 2. A Q24 is turned on at the leading of a signal phi7, the line, the inverse of BL charges a capacitor C2 of the circuit 1 to decrease the potential of BL, inverse of BL. The bit line potential (precharge potential) VBL in this case is set to 1/4Vcc by selecting the number of bit lines, the capacity and the capacitor C2. When the VBL is decided, the Q24 is turned off at the trailing of the signal phi7, the bit line pair is interrupted from a reference voltage V0, a Q23 is turned on at the leading of the signal phi6 to guarantee the level of the VBL at the circuit 2. Since the VBL is set lower, the potential difference between the H level (Vcc) of the signal phi2 of the WL line and the VBL of the bit line is large and the information transmission from a memory cell MC to the bit line is quickened. |
