| 摘要 |
PURPOSE:To make the handling of a system state tracer easy by providing the tracer with a memory circuit previously connected to a common system bus and its control circuit. CONSTITUTION:Necessary information is applied from a system bus to the memory circuit 1 as data and the system bus information is successively stored in the memory circuit 1 in each state cycle. When an event signal is applied to an operation control circuit 3, and circuit 3 switches writing operation to reading operation by regarding the state as the final storage information and also switches address information applied from a counter circuit 2 to that applied from a system bus 20. A read control circuit 4 is driven by a request from a CPU module 21 and the state information stored in the memory circuit 1 is outputted to the system bus 20. Consequently, the information excellent in the reproducibility of an event and extremely significant to event analysis can be obtained and its handing can be made easy. |
