发明名称 |
Latch-up protection circuit for integrated circuits using complementary mos circuit technology |
摘要 |
A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit connects a capacitor bias generator to the capacitor when a voltage on the substrate bias terminal is less than a sum of a reference potential and a threshold voltage of a first transistor in the electronic protection circuit. The electronic protection circuit disconnects the capacitive bias generator from the capacitor when a voltage on the substrate bias terminal is greater than the sum. During normal operation the electronic protection circuit does not load a supply voltage source or a substrate bias voltage source with current.
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申请公布号 |
US4791317(A) |
申请公布日期 |
1988.12.13 |
申请号 |
US19870025654 |
申请日期 |
1987.03.13 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT |
发明人 |
WINNERL, JOSEF;RECZEK, WERNER |
分类号 |
H01L27/08;G05F3/20;G11C11/407;H01L21/822;H01L21/8238;H01L21/8242;H01L27/04;H01L27/092;H01L27/108;(IPC1-7):H03K17/16 |
主分类号 |
H01L27/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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