| 摘要 |
PURPOSE:To output the video signal of a standard specification without using a picture memory block by supplying the driving signal of one CCD element, which has been shifted by one picture element in a vertical direction, to the other CCD element through one field delay reading circuit. CONSTITUTION:A timing pulse is generated from a synchronizing signal from a synchronizing signal generation circuit 17 in an electronic shutter driving circuit 15 and an interline type CCD element 13 is driven. On the other hand, the field delay reading circuit 16 processes the timing pulse from the electronic shutter driving circuit 15, generates the timing pulse executing a field delay reading action and drives a CCD element 14. At that time, the CCDs 13 and 14 are shifted by one picture element in the vertical direction and are adhered to a prism 12. The signals which have been read from the CCD element 13 at the timing of a first field, and the signals which have been delayed by one field and which have been read at the timing of a second field are combined and signal-processed in a process circuit 18, and a video signal output 21 is obtained.
|
