| 摘要 |
PURPOSE:To narrow the opening area of a groove or a hole and to reduce the occupying area of a semiconductor memory cell by forming a capacity element on a semiconductor substrate and a vertical field effect transistor in a semiconductor layer laminated on the substrate. CONSTITUTION:A groove is formed on a substrate 1, and a P<+> type stopper region 2 is formed under a groove. The surface of the groove is covered with a capacity film 3, and a space is filled with one capacity electrode 4. An epitaxial layer 5 is formed as a semiconductor layer on the substrate 1, and a single crystalline silicon is laterally grown on the film 4. A groove is further formed on the layer 5 above the groove, and a gate oxide film 7 and a gate electrode 8 are formed in the groove. An N<+> type layer 9 is formed on the surface of the layer 5, and connected to a bit line 11. Since the electrode 8 can generate a channel to the other electrode of the capacity element from the layer 9, the charge of the line 11 can be stored as charge in the capacity element. |
