发明名称 INTER-CPU INTERFACE CONTROL SYSTEM
摘要 PURPOSE:To simplify the constitution of an interface circuit as well as the software control by utilizing an idle channel of a communication control LSI to control a 1-chip CPU that secures a serial interface to a main CPU. CONSTITUTION:A communication control LSI 12 has two channels and performs the switch between a channel A (CH.A) and a channel B (CH.B) by a channel switch signal received from a CPU 11. Then the channel A of the communication control LSI 12 performs the normal communication control. While the channel B of the LSI 12 is originally idle and is used for control of the interface in this case. The main CPU 11 delivers a chip enable signal to actuate the LSI 12. As a result, the constitution of an interface circuit and the software control can be simplified.
申请公布号 JPS63298467(A) 申请公布日期 1988.12.06
申请号 JP19870133040 申请日期 1987.05.28
申请人 RICOH CO LTD 发明人 SAKASHITA TADAAKI
分类号 G06F13/38;G06F15/16;G06F15/17 主分类号 G06F13/38
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