发明名称 |
MANUFACTURE OF SEMICONDUCTOR DEVICE |
摘要 |
PURPOSE:To reduce source resistance without allowing gate capacitance to increase by a method wherein insulating side walls are tapered on the sides of a gate electrode and the gate electrode equipped with such side walls is used as a mask in a process of ion implantation. CONSTITUTION:An insulating film 34 is formed by bias-sputtering on a semiconductor substrate 30 mounted with a gate electrode 32. The insulating film 34 is selectively removed by reactive ion etching for the formation of tapered insulating side walls 30 on the sides of the gate electrode 32. The gate electrode 32 now provided with the tapered insulating side walls 36 serves as a mask in a process of impurity ion implantation. In this design, source resistance can be reduced without an increase in gate capacitance.
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申请公布号 |
JPS63296380(A) |
申请公布日期 |
1988.12.02 |
申请号 |
JP19870132237 |
申请日期 |
1987.05.28 |
申请人 |
SUMITOMO ELECTRIC IND LTD |
发明人 |
NAKAJIMA SHIGERU |
分类号 |
H01L21/265;H01L21/336;H01L21/338;H01L29/78;H01L29/80;H01L29/812 |
主分类号 |
H01L21/265 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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