发明名称 DEFECT DATA ENTRY CIRCUIT
摘要 PURPOSE:To enable accurate entry of defect data, by providing a Y-axis counter, a buffer memory or the like to prevent erroneous recognition of a Y-coordinates position. CONSTITUTION:A start pulse ST and a clock CLK are input inputted into an X-axia counter 11, detect data D11, D12... and D52 are inputted into an OR unit 12 from a defect detector 5 and a line synchronous signal PG is inputted into a frequency dividing circuit 13. A counter 11 counts the clock CL and counts outputs as obtained when a defect data is entered into an FIFO memory 22 as X-coordinates position data. Moreover, a unit 12 accumulates defect data for several scannings corresponding to each of the data D11, D12... and D52, counts the signal PG divided in frequency from the circuit 13, and outputs counts into the memory 22 as Y-coordinates position data when the defect data is inputted. In this manner, an X-coordinate position data, the defect data and the Y-coordinate positions data are stored temporarily into the memory 22. These data are transferred to a CPU7 with a DMA between memory 22 and a memory of the CPU7. This enables accurate entry of the defect data to prevent erroneous recognition at a Y-coordinates position.
申请公布号 JPS63295947(A) 申请公布日期 1988.12.02
申请号 JP19870129639 申请日期 1987.05.28
申请人 NIPPON SHEET GLASS CO LTD;YASKAWA ELECTRIC MFG CO LTD 发明人 OKAFUJI MASAHARU;ABE JUNICHI
分类号 G01B11/00;G01B11/02;G01N21/89;G01N21/896 主分类号 G01B11/00
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