| 摘要 |
PURPOSE:To easily make frame reception on a receiving side synchronous to the frame transmission on a transmitting side when frame transmission is made without changing the content of received data, by interrupting frame transmission and adding a frame checking sequence which is inverted by one bit to a frame being transmitted when an underrun or overrun is produced in the course of frame transmission. CONSTITUTION:When an underrun or overrun is produced in transmitting data at a processor interface (PINF) 9 while frame transmission is carried on from a transmission module (TMD) 6, the TMD 6 stops the frame transmission. After the one bit of the frame check sequence (FCS) in the frame being transmitted is inverted and added to the interrupted sequence as an abnormal frame check sequence (EFCS), the transmission is started. The added abnormal frame check sequence can perform '0' insertion and removal. Since the frame can be converted into parallel data at a reproducing transmission circuit (REP) 4, therefore, the frame can be transmitted again synchronously to a transmission flag pattern F at the TMD 6.
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