| 摘要 |
PURPOSE:To improve testing efficiency by reading out data stored in different memory cells in parallel through a 1st switching circuit for only reading and a 2nd switching circuit for only writing and applying the compared result to the external. CONSTITUTION:In a testing stage, the data of the same level are previously written in all memory cells MC. At the time of sequential reading, the data stored in the different memory cells MC are simultaneously read out in parallel only by one addressing through the 1st switch circuit CW1 for only writing in normal operation and the 2nd switch circuit CSW2 for only reading and the compared result is applied to the external. Since the writing route which is not utilized for data reading in the normal operation can be utilized for data reading in parallel with the data reading operation at the time of testing, the testing efficiency can be improved.
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