发明名称 |
BINARY MULTIPLIER CIRCUIT |
摘要 |
An improved integrated circuit multiplier employs modified Booth's recode techniques on a portion of a multiplier word, the output of two or more such multipliers being incorporated according to the invention to eliminate a source of error associated with the prior art. |
申请公布号 |
JPS63292324(A) |
申请公布日期 |
1988.11.29 |
申请号 |
JP19880113419 |
申请日期 |
1988.05.10 |
申请人 |
UNITED TECHNOL CORP <UTC> |
发明人 |
REONAADO FUAINGOORUDO |
分类号 |
G06F7/53;G06F7/52;G06F7/533 |
主分类号 |
G06F7/53 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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