| 摘要 |
PURPOSE:To attain the transfer of a consecutive data block by using a FIFO applying data input/output timing asynchronously and adding a control signal representing the section for each block so as to easily discriminate the end of data block. CONSTITUTION:The titled system consists of a transmitter 10 sending a data for each block comprising a CPU 1, a ROM 2 and a RAM 3, a FIFO 4 applying data input/output asynchronously, a repeater 20 comprising an input control circuit 5 outputting the control signal changed in receiving the final data of each block of the transfer data to the FIFO 4 and a receiver 30 receiving a data from the FIFO 4. A transfer data is written in a FIFO 4 from a RAM 3 under the control of the CPU 1 and when the CPU 1 discriminates the end of the block, it is informed to the circuit 5, the control signal is outputted from the circuit 5 and written in the FIFO 4 together with the data. The receiver 30 uses the output controller to read the data entirely and individually from the input side.
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