| 摘要 |
PURPOSE:To enable a high speed data transmission by providing a circuit which informs a maskable and an unmaskable interruption requests to request a data processing, and the circuit which prohibits the next maskable and unmaskable interruption requests, while an unmaskable interruption is executed. CONSTITUTION:When the output of an OR circuit 6 is H and the output of a busy circuit 9 comes to H as well, an AND circuit 10 comes to H, and informs the occurrence of the unmaskable interruption NMI of a computer 1. The signals 13a, 13b of a command decoder circuit 13 are the signals outputted by the control of the computer 1, and are inputted to the busy circuit 9. When the output signal, the inverse of BUSY of the busy circuit 9 is energized, the AND circuit 10 comes to be closed, and it is displayed in the computer 1 that it is in a busy state, and it is prohibited for other unmaskable interruption NMI to occur freely during it. The busy state of the computer 1 continues from a processing to reset a transmission reception controller TRC mask till a processing termination IRET, and it is prohibited for other unmaskable interruption NMI to occur without any restriction during it. |
