| 摘要 |
An input signal level detecting circuit includes a first inverter group circuit having first and second inverters connected in series, and a second inverter group circuit having third and fourth inverters connected in series. The input terminals of the first and third inverters are supplied with a signal having first and second levels to be detected. The output terminals of the second and fourth inverters are connected to set and reset terminals of the flip-flop circuit. When the mean level of the first and second levels is VTM and the threshold voltages of the first to fourth inverters are VT1 to VT4, respectively, the relations VT1>VTM; VT2<VTM; VT3<VTM and VT4>TTM are satisfied.
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