发明名称 METHOD FOR LOCKING PLL CIRCUIT
摘要 PURPOSE:To attain quick locking in changing over an object of synchronization by resetting a phase of an input signal so as to make the initial phase error zero when a reference horizontal synchronizing signal or a regenerative horizontal synchronizing signal is selected as other input signal to a phase comparator. CONSTITUTION:A phase comparator 22 detects a phase error between a clock of a horizontal scanning frequency fH obtained from the frequency-division of an output of a voltage controlled oscillator VCO 30 and a reference horizontal synchronizing signal by a digital value. A control circuit 20 monitors an output of the phase comparator 22 and regards it to be in the locking state that the phase error reaches the range W1 n2 times consecutively within n1.H (H is a horizontal scanning period) from the locking start of the synchronization. In this case, when a video signal is regenerated, a control circuit 20 throws a selector 21 to the position (b) to select the regenerative horizontal synchronizing signal. Simultaneously, the phase of the signal of horizontal scanning frequency fH being the frequency division output of the N2 frequency divider 32 is set to make the initial phase error of the phase comparator 22 zero with respect to the regenerative horizontal synchronizing signal.
申请公布号 JPS63286082(A) 申请公布日期 1988.11.22
申请号 JP19870121841 申请日期 1987.05.19
申请人 PIONEER ELECTRONIC CORP 发明人 MORIYAMA YOSHIAKI
分类号 H04N5/956;H03L7/10;H03L7/14;H04N5/95 主分类号 H04N5/956
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