发明名称 MACHINE CHECK HALT PROCESSING SYSTEM
摘要 PURPOSE:To realize the error recovery processing via software when the reading is carried out in division by stopping the working of a CPU only when an error is produced again before an error flag is cleared by the error recovery processing after a first error is produced and a vector request signal or vector answer signal is outputted. CONSTITUTION:A machine check enable flag 2 is reset by a vector request signal or a vector answer signal. Then a CPU receives the information of the vector answer signal to complete the prescribed recovery processing and informs an error clear signal to an error flag 1. When an error signal (parity error signal) is informed again before the flag 1 is reset, a machine check halt flag 3 is set and the working of the CPU is stopped. Thus it is possible to read plural memories with a single instruction and to secure the chances for recovery of errors even if the errors are produced continuously.
申请公布号 JPS63285641(A) 申请公布日期 1988.11.22
申请号 JP19870120238 申请日期 1987.05.19
申请人 FUJITSU LTD 发明人 YAMAGUCHI MASAHIKO;HIROTA YASUO
分类号 G06F11/00 主分类号 G06F11/00
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