发明名称 ERROR CORRECTION CODE GENERATING SYSTEM
摘要 PURPOSE:To obtain check codes and syndrome codes for all data bit patterns only by the delay of memory access time by allowing data bit to correspond to the address bits of a memory and previously storing the check codes and the syndrome codes in the memory. CONSTITUTION:A check code 0 bit is obtained by inputting 14 data bits, i.e. data bit 0-7, 14, 19, 22, 24, 30, 31 to the address bits A0-AB of the memory 11. When the 14 data are inputted to the corresponding address bit of the mem ory 11, the data of the corresponding memory addresses are outputted to an output CO0/S0 of a bit generating circuit 1. Thus, check codes for the combinations of all data can be obtained by previously storing the check codes corresponding to the data in the memory 11. Bit generating circuit 2-7 corre sponding to bits 0-6 are similarly constituted.
申请公布号 JPS63282851(A) 申请公布日期 1988.11.18
申请号 JP19870118402 申请日期 1987.05.15
申请人 NEC CORP 发明人 TANABE YOSHIICHI
分类号 G06F11/10 主分类号 G06F11/10
代理机构 代理人
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