| 摘要 |
PURPOSE:To improve processing performance by updating the address of an individual memory in a processor by '+1' and executing the reading of the contents of the individual memory and the writing of receiving data from a bus in the memory based on the held address. CONSTITUTION:A memory control device 3 receiving the setting by an address control circuit 9 executes the outputting operation of data to a bus 100 or the writing operation of data from the bus 100 to the memory by the number of transfer words while updating the address one by one by a '+1' updating circuit 10. At the time of detecting the execution of transfer operation by the number of transfer words, the control circuit 9 reports a transfer end to a control part 1 and resets a transfer mode display FF 4 and a started mode display FF 11. Consequently, the reduction of processing performance can be suppressed.
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