| 摘要 |
PURPOSE:To simplify a circuit by successively inputting flag selecting results by means of an n2-input multiplexer in the order of the flags of an objective CPU, successively shifting the results based on a shift clock signal and finally forming the flags of the objective CPU. CONSTITUTION:When flags corresponding to the flags D of the objective CPU are selected out of the flags C (n2 pieces) of a virtual CPU inputted to the n2-input multiplexer 2 are selected based on a virtual CPU flag selecting signal A, the values of the flags are outputted from the multiplexer 2 and inputted to a shift register 1. When the shift clock signal B id driven, the contents of the shift registers 1 are shifted to the left one by one bit and the value inputted in the register 1 is set up in the most right side bit in the register 1. Said operation is successively repeated from the left side flag of the flags of the objective CPU by n1 times and the flags D of the objective CPU are finally set up. Consequently, the device can correspond to various objective CPUs and the circuit can be simplified.
|
