| 摘要 |
<p>A synchronizing clock signal generator has, in combination with a PLL circuit, a signal delay circuit (1) for delaying a reference input signal by a prescribed time and issuing a reference signal, and a shift register (2) receptive of the reference input signal and a clock signal which is an oscillation signal from a voltage controlled oscillator (5) or a signal produced by frequency-dividing (6) the oscillation signal by an integer, for issuing a comparison signal in synchronism with a clock signal. The comparison signal and the reference signal are compared in phase. Even if the reference input signal is not a pulse signal of a fixed frequency, a synchronizing clock signal can be reproduced, insofar as the reference input signal is a pulse signal with its polarity inverted at the time of a multiple of a prescribed natural period.</p> |
