DIGITAL PHASE LOCK LOOP

摘要

A digital phase lock loop utilizing a programmable delay line (12) to phase shift the output of a crystal (10) generated reference clock signal and lock it to digitized data transitions recorded on a suitable medium is provided. The output of the delay line (12) is compared to the digitized data transitions in a phase detector (14) to determine if the delay line (12) output leads or lags the data transitions. The delay line (12) is then programmed by an up/down counter circuit (161,163) to reduce the phase difference between the data transition and the delay line (12) output to a minimum value.