| 摘要 |
PURPOSE:To shorten a distance between a contact hole for a transistor and a gate electrode, and to reduce the area of a memory cell and improve the degree of integration by forming the contact hole for a memory-cell bit line onto flattened polycrystalline silicon shaped so as to be superposed on the gate electrode. CONSTITUTION:First layer polycrystalline silicon formed onto a p-type silicon substrate 1 through thin gate insulating films 12 or gate electrodes 3 as word lines for a memory cell are coated with insulating films 14 consisting of SiO2, etc., shaped in a self alignment manner. Polycrystalline silicon 6 is shaped to a storage capacitance section and polycrystalline silicon 8 as upper electrodes onto the polycrystalline silicon 6, and a contact hole on flattened polycrystalline silicon 61 is formed extending over the upper sections of the gate electrodes 3 in the contact section of a bit line. A MOS transistor has low-concentration drain structure, and source.drain regions 4, 5 being in contact with polycrystalline silicon 6, 61 are shaped in high-concentration n-type regions. Margins among the contact hole and the word lines 3 can be brought to zero. |
