发明名称 CLOCK REGENERATION CIRCUIT
摘要 PURPOSE:To prevent a circuit from being reset at the time of the signal omission of short time, and to make it pull in at high speed at the time of the switch of a signal source as well by performing the decision of a step-out by means of a reset circuit to perform it on the basis of a synchronizing signal, the pass band control circuit and the latch circuit of the output signal of a horizontal phase comparator, and a loop filter. CONSTITUTION:An FP phase comparator 4 compares the phases of an FP and the regenerated FP, and supplies them to the reset circuit 13. An FP omission detection circuit 5 supplies its output to the reset circuit 14. Thus, the step-out between the regenerated FP is detected, and when it exceeds a standard, a regenerated HD generation circuit 11, a regenerated FP generation circuit 12 and the loop filter 7 are set at an initial state by using the circuits 13, 14 and a logical sum circuit 15. The circuit 13 resets the loop filter 7, etc., when the FP in the input signal, detected during the continuous duration of the detected step-out, reaches the prescribed number of times. Therefore, it is reset for the first time, when the FP in the input signal is omitted extending over comparatively long time. Besides, since at the time of the switch of the signal source, the FP is detected continuously during the duration of the step-out state, it is quickly reset.
申请公布号 JPS63279674(A) 申请公布日期 1988.11.16
申请号 JP19870115077 申请日期 1987.05.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAWAHARA ISAO
分类号 H04N5/05;H04N5/12 主分类号 H04N5/05
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