| 摘要 |
PURPOSE:To improve a response speed and to reduce a circuit scale by providing a lower limit mask generating circuit for generating mask, data, an upper limit mask generating circuit and a logical circuit at respective prescribed bit positions. CONSTITUTION:The lower limit mask generating circuit 21, generates the mask data in which values from the bit position 0 to the bit position i-1 is '0', for instance when the lower limit value (i) is designated and the value of other bit positions is '1'. The upper limit mask generating circuit 2 generates the mask data in which the value from the bit position 0 to a bit position (j) is '1' when the upper limit value (j) is designated and the value of other bit positions is '0'. Consequently, the AND of the respective mask data of the circuits 21, 22 is operated by the logical circuit 23 to obtain a bit mask. Accordingly, a shifting operation is not required to enhance the reponse speed. Since the circuits 21, and 22 can be constituted of a single ROM and the function of the circuit 23 can be incorporated in the ROM according to a wired AND, the circuit scale can be reduced.
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