High speed/high drive CMOS output buffer with inductive bounce suppression

摘要

An output buffer is disclosed which employs a first pair of transistors connected in an (N-channel over P-channel) totem pole configuration, a second pair of transistors connected in a (P-channel over N-channel) totem pole configuration in parallel with the first pair of transistors, and a pair of inverters connected to delay the drive to the second pair of transistors.