发明名称 TESTING DEVICE FOR INTEGRATED CIRCUIT
摘要 PURPOSE:To change an application state by a small number of memories, by changing an application state of a test pattern, based on a value of a counter which is counted up in accordance with a clock. CONSTITUTION:A clock generated by a rate generator 21 is supplied to a buffer memory 22 through an address counter 21A, and from the buffer memory 22, an input data and an expected value data are supplied to a waveform formatter 27A and a comparator 27B, and also, supplied to a pattern counter 23. Subsequently, an output of the pattern counter 23 is compared with values of pattern counting value designating registers 24A, 24B by collators 25A, 25B and based on its outputs C0-C2, a prescribed timing is generated by a timing data output circuit 26, by which an application state to an integrated circuit 28 to be tested, of an input test data and an output expected data is changed.
申请公布号 JPS63271180(A) 申请公布日期 1988.11.09
申请号 JP19870104545 申请日期 1987.04.30
申请人 FUJITSU LTD 发明人 TOKUYAMA SABURO
分类号 G01R31/28;G01R31/319;G01R31/3193 主分类号 G01R31/28
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