| 摘要 |
<p>PURPOSE:To secure pulse width and to prevent a system from malfunctioning at the time of the switching of a clock signal by providing a delay circuit which delays the output signal from a switching circuit and inputs it to a gate means. CONSTITUTION:The delay circuit such as a flip-flop controls the switching timing of the clock. Namely, the current output levels of clock signals 12 an 13 are equalized to the output levels at the time of switching and after the necessary pulse width of the level is secured, the switching is performed. Consequently, the pulse width of the level is secured and further the output width of the other level is secured as long as the pulse width of the clock signals 12 and 13. Then when plural clock signal sources suffice the rule of the pulse width of a CPU, the rule of minimum pulse width can be followed even at the time of the clock switching.</p> |
