| 摘要 |
<p>A latch circuit provides for a reading of a state of an EPROM cell and retains that state after the reading sequence is completed. The memory state of the EPROM is inputted to a NOR gate during a power on reset condition. The output of the NOR gate is fed back through an inverter to the input of the NOR gate, such that when the EPROM is deactivated, the input of the NOR gate is latched to the previous EPROM memory state.</p> |
