| 摘要 |
PURPOSE:To obtain a circuit to generate an address for the decoding of a code word, by constituting an address generation circuit for the decoding of the code word consisting of data and an error correction code of a logic circuit operated according to the arranging constitution of the code word. CONSTITUTION:A leading address H from which the synchronizing signal of a block to be decoded is eliminated is outputted from a readout address pointer 20 for the decoding. The address H of one preceding block is read from a pointer 12a at every block, and the decoding of one preceding block is performed. To an address bus, the write address WRA of a buffer RAM or a readout address from the buffer RAM outputted from a full adder 21 is outputted selectively by a timing signal. A signal (p) inputted to the adder 21 is an LSB/MSB brain selection signal, and it is represented as '0', or '1'. A signal L which represents a symbol position is also inputted to the adder 21, and as a result, an address signal (H+2L+p) is outputted from the adder 21.
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