| 摘要 |
PURPOSE:To minimize an influence caused by the delayed time of signal propagation and to realize a high speed of a system as a whole by a method wherein two or more memory circuits are arranged in a control part having a function of signal processing in such a way that they are of tiered structure according to the sequence required for a high-speed operation from a geometrically adjacent position. CONSTITUTION:A memory control circuit SCONT1 is arranged in the central part of a wafer WSI; buffer memories BM are arranged on both sides of the circuit. Circuit devices such as MOSFET's and the like which are formed in a circumferential part of the wafer have a tendency that their channel length is shortened; because their conductance is big, they operate at high speed. By this setup, an operating speed of the memory circuits themselves which are arranged in the circumferential part of the wafer WSI is fast; the speed of the memory circuits themselves becomes slow according as they are arranged near the central part. On the other hand, a signal transfer route of a write/read signal in the memory circuits in the circumferential part of the wafer WSI is long; it becomes short gradually as it approaches the central part. Accordingly, the operating speed of all the memories at an identical level can be averaged and a high speed operation is achieved.
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