| 摘要 |
<p>PURPOSE:To prevent the generation of a spike or an abnormal pulse width clock, in an output clock by preventing the clock, previously outputted, by a gate circuit, and after waiting this, making the clock, instructed to be outputted next, pass through it. CONSTITUTION:A flip-flop circuit 1 which latches a select signal SEL of n-bits at the selected clock CLKO, and a decoder 2 which decodes the output of the said circuit 1, and a gate opening closing circuit 3 which generates the respective gate signals of quite asynchronous input clocks CLK, and a gate circuit 4 are provided. The selected signal SEL is latched at the leading edge of the output clock CLKO, and the clock, previously outputted, is prevented by the circuit 4 at the timing of its trailing edge, and after waiting this, the clock of other side passes through the gate circuit 4 at the timing of its trailing edge. Thus, the spike or the abnormal pulse width clock is never generated in the output clock CLKO.</p> |
