| 摘要 |
PURPOSE:To improve the processing speed for the defective data by providing the registers of plural bytes on plural buses at every input/output line set for a data buffer and adding an address circuit and a timing control circuit against those registers. CONSTITUTION:The write data are written into plural divided addresses of a data buffer 9 via a register 3 and a pre-register 4. When a prescribed quantity of the write data is fetched, the control information is added to the write data. Then this write data is sent to an optical disk drive. When a read instruction is received, the output received from an error correcting circuit 13 is written into the buffer 9 via a register 11 and a pre-register 10. When said output reaches a prescribed quantity, an access is given as necessary to the buffer 9 via a register 16 and a pre-register 17 based on the error correcting information. Thus an error is corrected. Then the data are sent to a host interface control circuit 1 via the pre-register 4 and the register 3.
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