发明名称 Memory control method and apparatus
摘要 A memory control method and apparatus useful in an input/output buffer memory of a multistation system. The buffer memory storage locations are dynamically divided into a plurality of unit groups having varying storage capacities, and flags are provided which indicate whether or not units are in use. When buffer memory is requested, the size of the requested area is divided by the size of a unit to determine the number of units required and a bit pattern indicating this number is provided. The bit pattern is successively compared and shifted with respect to the flags until the required number of adjacent unused units is found.
申请公布号 US4780815(A) 申请公布日期 1988.10.25
申请号 US19870016519 申请日期 1987.02.17
申请人 HITACHI, LTD. 发明人 SHIOTA, KENJI
分类号 G06F13/38;G06F3/00;G06F5/06;G06F12/02;G06F13/10;(IPC1-7):G06F12/00 主分类号 G06F13/38
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