| 摘要 |
PURPOSE:To prevent the occurrence of a latch-up phenomenon even when a power source is turned on by a method wherein the output terminal of a substrate bias generating circuit is short-circuited to a grounding level for the prescribed period after the power source has been turned on. CONSTITUTION:The title integrated circuit has the first N-channel type MOS transistor Q3 and the second N-channel type MOS transistor Q4 having the threshold voltage lower than that of the transistor Q3. At this point, a high level pulse signal is generated during the prescribed period after a power source is turned on. As high level voltage is applied to the gate of the first transistor Q3 through the intermediary of a capacitor 2, the first transistor Q3 becomes conductive for the prescribed period immediately after the power source is turned on, and the main section (time t2-t3), in which the potential VPB of an output terminal PBB indicates a positive value, is forcedly clamped 0V. Consequently, the occurrence of a latch-up phenomenon can be prevented. |
