| 摘要 |
PURPOSE:To attain a trigger signal generator operated at a rate of parallel stream by providing a means detecting a parallel stream cycle of trigger signal and a means detecting the bit of parallel stream corresponding to the trigger signal in the cycle. CONSTITUTION:N-stage binary counter receives a clock in the rate of a parallel stream by using a clock signal of a line 20 and counts down by a cycle length of 2N-1 and a block 21 detects the condition that (N-M) bits of low-order in the 1st section 17 of the counter are all zero and sends the output to a line 22. The 2nd section 18 of the counter whose high-order is M-bit repeats the count down from 2M-1 to 0. A signal on the line 22 is used to instruct the clock cycle generating the trigger signal and the high-order M-bit is used to decide to which high rate bit the trigger signal corresponds. Thus, the components operated by the high rate clock are decreased.
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