| 摘要 |
PURPOSE:To efficiently carry out timing adjustment without taking the fluctuation of the gate delaying time of a memory IC into account, by forming pulses which are delayed by a fixed time. CONSTITUTION:The cycle of clock signals 25 is set at the 1/2 of a writing cycle TWC. At the time of high-speed operations when the clock cycle is shorter, shaping of pulses is not carried out at a writing pulse producing circuit 26 and write designating information 38 becomes writing pulses 42 as it is. At the time of intermediate- and low-speed operations, moreover, writing pulses 43 are produced by extending the time (t) which is required for changing the information 38 from '0' to '1' by waveform shaping in order to delay the rise of the pulses at the circuit 26 and timing adjustment is performed. In such way, the pulses 42 or 43 are supplied to the writing control inputting section WE of a memory cell array 21 from the output side of the circuit 26.
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