发明名称 NETWORK USING MICROPROCESSOR OR THE LIKE
摘要 <p>PURPOSE:To make it possible to connect also an element with slow response time by providing a network with a data temporary holding circuit connected to that held data are outputted to a bus based on an access from a microprocessor or the like. CONSTITUTION:Data on a data bus 3 are acquired and held in the temporary holding circuit 10 for data with a small set-up time at the leading edge part of a data reading signal 4. When an access signal 6 to the circuit 10 is outputted from the microprocessor 1 or the like, the circuit 10 starts to output data held in the data bus 3. Since the microprocessor 1 or the like sufficiently satisfies the set-up time, accurate reading can be attained. Namely, the microprocessor 1 or the like reads out data from an element 2 with a slow response time at first, deletes the read data and then reads out data from the circuit 10 to treat the data as the one obtained from the element 2.</p>
申请公布号 JPS63250758(A) 申请公布日期 1988.10.18
申请号 JP19870085460 申请日期 1987.04.07
申请人 NEC CORP 发明人 YONEDA KAZUHIRO
分类号 G06F13/38;G06F15/78 主分类号 G06F13/38
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