| 摘要 |
PURPOSE:To prevent the generation of a false stable point, and to ensure a synchronization by making a signal for the synchronization not to be generated at a transmission side, and providing a non-linear circuit in the delaying lock loop of a receiving side, and making the control signal of a false noise code generating clock flow in the said circuit. CONSTITUTION:The non-linear circuit 13 is inserted between the subtracter 9 of the delaying lock loop 10 and a VCO 12 of the receiving side. The circuit 13 is constituted of diodes D1, D2 and resistors R1, R2 as shown in a figure. The resistance values are in the relation of R1-R2. When it is assumed that the voltage drop portions of the diodes D1, D2 are Vd1, Vd2 respectively, and a forward voltage is Vp in a case that the output signal of the subtracter 9 is a positive level, and a reverse voltage of Vn in the case that the output signal of the subtracter 9 is a negative level, the output voltage Vout of the circuit 13 comes to be the voltage that the respective voltage drop portions Vd1, Vd2 are subtracted from the input voltages Vp, Vn of the circuit 13, and accordingly, even if a chevro shaped waveform is contained in the output signal of LPFs 7, 8, the synchronizing signal of the waveform, in which only a stable point is generated and no false stable point is generated, can be supplied to the VCO 12. |
