| 摘要 |
PURPOSE:To prevent the increase in a random circuit causing a hindrance to large scale circuit integration (LSI) by increasing the signal rate of an input signal, applying arithmetic operation such as addition and multiplication in the rate, feeding back result of addition delayed by plural delay elements in the process of the arithmetic operation and inputting the result again to an adder circuit. CONSTITUTION:As selector control signals 1-6, 1-7 change to 00, 01, 10, 11, 1st, 2nd, 3rd and 4th inputs are selected sequentially from the upper part and the result is outputted respectively to signal lines 1-11, 1-12. Thus, signals A-D and G-H appear at the signal lines 1-11, 1-12 at a rate being four times the phase of the original signals A-H. A signal retarded from the signals for the signal lines 1-11, 1-12 by one clock CK2 appears at the signal lines 11-13, 11-14. The signals are added by an adder 1-2 and a signal appears at a signal line 1-16. The signal of the signal line 1-16 is subjected to coefficient multiplication by a coefficient multiplier 1-5. Thus, a 7-tap linear phase linear digital filter suitable for large scale integration with considerably less random circuits is obtained.
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