发明名称 INTERFACE CIRCUIT
摘要 PURPOSE:To output a page synchronizing signal, an image synchronizing signal and a serial image signal synchronizing with the synchronizing signals by converting parallel image data to serial image data, synchronizing with a clock signal by a generating means and generating the synchronizing signal of the serial image data. CONSTITUTION:When the output of image data is instructed, data are outputted to a data bus 8 and a writing signal/WP1 is outputted. Next, in order to turn on an image synchronizing signal VEN 105, the data bus and the writing signal/WP1 are outputted. From a memory, etc., the image data of 8 bits are read by one byte, a writing signal/WP2 is outputted and latched to a register 5. Thus, one-byte data are converted to serial data by an interface circuit 101, synchronized with a clock CLKE 106 and outputted to a coding circuit 100. Thus, parallel image data can be converted to the serial image data, synchronized and outputted together with the synchronizing signal and the synchronizing clock signal, and therefore, respective types of the signal can be supplied to the coding circuit.
申请公布号 JPS63248281(A) 申请公布日期 1988.10.14
申请号 JP19870081275 申请日期 1987.04.03
申请人 CANON INC 发明人 MURATA YUKIO
分类号 H04N1/413;G06T1/60;H03M9/00 主分类号 H04N1/413
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