| 摘要 |
A multi processor system in which processors (5, 6) communicate via a bus (7) with ordered access of the processors to the bus. After receipt of a trigger signal (e.g. via 1, 2, (3, 4) each triggered processor times its access to the bud dependent on its unique code (which may be its address) and the function the processor is to perform. In a special case in a first phase several processors transmit information along the bus in a queued manner to a receiving processor which infers the processor transmitting the information it is reading from the time lapse from the trigger signal; in a second phase a processor transmits information onto the bus in a queued manner and each receiving processor by timing its reading of the bus reads the information intended for it. An application of the invention in intra-shelf communication in a private branch telecommunications exchange is described. |
