发明名称 POLYPHASE CLOCK GENERATING CIRCUIT
摘要 PURPOSE:To form an optional duty ratio waveform in the same hardware constitution by varying an integration coefficient of an integration circuit, quantity of integration (DC voltage), a hysteresis width of a hysteresis comparator, and a threshold voltage. CONSTITUTION:A switched capacitor integration circuit is used for the integration circuit, its integration coefficients C2/C1 are programmed and one hysteresis comparator is provided, the hysteresis width VH is programmed and values of DC power supplies VB1, VB2 are programmed to obtain an optional frequency division ratio. The output of the integration circuit obtained in such a case is supplied to a 2nd hysteresis comparator, then the duty ratio output having the resolution of 1/frequency division ratio is obtained by the setting method of the threshold voltage of the hysteresis comparator.
申请公布号 JPS63246918(A) 申请公布日期 1988.10.13
申请号 JP19870081505 申请日期 1987.04.01
申请人 NEC CORP 发明人 YOSHIDA OSAMU
分类号 H03K5/13;H03K5/133;H03K5/15 主分类号 H03K5/13
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