发明名称 MOS TYPE SEMICONDUCTOR ELEMENT
摘要 PURPOSE:To reduce the irregularity of the whole capacity by forming large unevenness on a floating gate electrode to increase the value of a capacity between electrodes. CONSTITUTION:A first floating gate electrode region is patterned by a photolithography technique and an etching technique. Then, when the photolithography and dry etching techniques are again used to remove by etching the region of a recess 5 so that a remaining polycrystalline silicon film containing an impurity becomes 1000-7000Angstrom , floating gate electrode recesses 5 and protrusions 6 are formed. Then, a control gate electrode 8 is formed through an interlayer insulting film on the recesses 5 and the protrusions 6, and a control gate electrode 8 is made uneven in coincidence with the uneveness of the gate electrode. Thus, since a capacity between the gate electrodes can be increased, the irregularity of an electric field to a tunnel oxide film 4 can be reduced.
申请公布号 JPS63244686(A) 申请公布日期 1988.10.12
申请号 JP19870078059 申请日期 1987.03.30
申请人 NEC CORP 发明人 MATSUDA HAJIME
分类号 H01L21/8247;H01L29/78;H01L29/788;H01L29/792 主分类号 H01L21/8247
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