发明名称 DATA MAINTAINING CIRCUIT FOR SIGNAL PROCESSING CIRCUIT
摘要 PURPOSE:To prevent malfunction with a very simple circuit by coupling an disconnecting circuit of a power supply having an error corresponding to a reset signal in interlocking with ON/OFF state of driven power supply. CONSTITUTION:An disconnecting circuit 2 is inserted on the way of an error side power terminal +Vcc at input/output in drive power supply terminals +Vcc, -Vcc of a data input/output circuit 1. In applying driving power supply till the circuit is made stable, an inverted reset signal is supplied, the disconnecting circuit 2 is operated and no +Vcc is applied to the data input/ output circuit 1. When the circuit is made stable and no reset signal exists, the circuit 2 is turned on and the +Vcc is supplied to the data input/output circuit 1. Thus, the circuit starts from 0V and not from a positive voltage. The inverted reset signal is supplied also at the time of turning off the driving power supply, the circuit 2 is operated, the +Vcc is shut off and the circuit does not rise up to the positive value.
申请公布号 JPS63245120(A) 申请公布日期 1988.10.12
申请号 JP19870079273 申请日期 1987.03.31
申请人 FUJITSU GENERAL LTD 发明人 EBINE YOSHIAKI
分类号 H03K17/16;H03K17/22 主分类号 H03K17/16
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